In data-handling systems it is frequently necessary to utilize a number of independently operating processors complementing one another in the performance of a common task, e.g. the establishment of a telecommunication link.
Conventional equipment facilitating the exchange of messages in a multiprocessor system allows the interconnection of only two data processors at a time, the equipment being thus inaccessible to other processors during that period. Such equipment may be a bus or a memory associated with an arbitration device serving to determine the order in which requests for acess from different processors can be satisfied.
The temporary denial of access to other processors results in the formation of waiting queues which adversely affect the operating speed of the system. Controlling these queues and programming the arbitration device requires relatively complex additional circuitry. Moreover, the operating capacity of such a device limits the number of processors to be included in the system.